Re: A Startup Looking for IC Layout Designer/Lab Technician -- DPUG Message Board

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Subject: Re: A Startup Looking for IC Layout Designer/Lab Technician

Author:
Jeffrey N. Lear

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Date Posted: 22:04:52 05/14/04 Fri
In reply to: Lisa Dao 's message, "Re: A Startup Looking for IC Layout Designer/Lab Technician" on 03:09:08 03/27/03 Thu

Heads up!
I'm an extremely fast and excellent Sr. Mask Designer with over 35+ years experience... I'm incorporated and have been on contract to Sun Microsystems for the last 11 years. I have References from the Director of Engineering; Mask Design Supervisor(s); and Lead Design Manager(s). Prior to Sun, I contracted for Intel for 10 years and worked on ALL the x86 machines from 8186, to the Pentium. Master in Unix C-Shell programming, Skill code, and general aliases to eliminate unnecessary typing. I've been known to be called "The Best" by every Engineer I've ever worked with.
Tons of references... I'm the best at my trade, and I want to work with a team that knows that they have it all together and THEY ARE THE BEST TOO! Amen! ;=)

>LISA DAO
>1442 PIEDMONT RD
>SAN JOSE, CA 95132
>Cell Phone: 408-888-0073
>
>OBJECTIVE
> Seeking for a Senior Mask Designer or IC Layout
>position (CMOS,BIPOLAR,BICMOS) with 10 years plus
>experiences .
>EDUCATION
> BS BIOCHEMISTRY in SAN JOSE STATE UNIVERSITY
> AA degree (CMOS Mask Design) in SAN JOSE CITY
>COLLEGE
>QUALIFICATIONS
> USING CADENCE OPUS, UNIX, IC EDITOR, IC MAGIC ,
>L-EDIT, layout 3D GRAPHIC CHIP, PLL CHIP, ASIC CHIP,
>RAMBUS CHIP, IMAGE CHIP.
> VERIFICATION DATA and DEBUG errors by using
>DRACULA,DIVA, TANNER TOOL
> ( DRC, LVS,ERC, DBCOMPARE, and writing new
>technology file for DRC and LVS ).
>WORK HISTORY
>4-99-present: MASK DESIGNER ENGINEER,
>FAIRCHILDSEMICONDUCTOR CORP.
> Prepare floor plan, Estimate Chip Size, Block design,
>In charge Project
> Layout standard cell library for different CMOS
>technologies
> Layout from cell level to chip level of
>ANALOG/DIGITAL and MIX SIGNAL VLSI circuit from
>beginning to tape out .
> ANALOG and MIXED SIGNAL: Amplifiers, Data
>Conversion, Switching Regulators, Timer, PLL, VCO,
>BANDGAP,FILTERS.
> BICMOS: NPN, PNP, DIODE
> MICROCONTRLOLLER : ACE1502 (EEPROM, SRAM)
> Performed P & R of Block and chip level
> Debug errors by using DRACULA, DIVA ( DRC, ERC,LVS)
>10-98-3-99: SENIOR MASK DESIGNER , PERIPHERAL IMAGING
>CORPORATION
> Custom layout IMAGING CHIP from the cell level to
>the chip level with 128,250,480 pixels
> Writing and Modifying DRC rule follow new technologies
> Delivery layout and Responsible chip to tape out on
>time.
> Modifying old chip to make new chip .
> Verification data and debug errors by using TANNER
>TOOL ( DRC, LVS ).
>2-93-6-98: MASK DESIGNER ,PHASELINK LABORATORIES INC
> Custom layout : SRAM64-BIT, ROM64-BIT, ESD
>PROTECTION, DACSEN, FILTER,
> Performed P & R of Block and chip level
> Debug errors by using DRACULA,DIVA ( DRC, LVS,
>DBCOMPARE )
>PERSONALITY: Hard working, Good communication,
>Excellent team work.
>REFERENCE: Available upon request

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