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Date Posted: 09:16:27 12/09/01 Sun
Author: Jain
Subject: This should be read by everyone atempting to build 3 chip
In reply to: Tom 's message, "Re: AGC fix Schematic" on 17:34:08 12/02/01 Sun

Here we start again
What Tom said (message below) is extremely important: for the 3 Chip schewmatic the input level of 1 Vp-p (synchro included) is a MUST.
This is important because some versions of the schematic do not have the 75 ohms resistor to match the impedance of the video output (it depends of course if you install it in or outside a VCR or another device), and usually the level after the first trap is higher. I noticed also that my cable adapter (where I tested the device) has an IF circuit (KA 2914B, not in production anymore, and impossible to find on internet --unless you are ready to pay some money
--I had to reverse engineer the schematic to adapt my device) that doesn't handle too well the missing Hsynchro and the 47-100uF capacitor also doesn't help too much, so the use of the sampling circuit might be also a must. My circuit (I reprogramed the code) works fine on unscrambled channels, but is unstable on scrambled channels. I notice also that Canton 3 input amplifier is not perfect (the 18k resistor should be actually 16K) and someone should be carefull when using it (troubleshouting page must always be considered, it is very helpfull). Probably the Canton 5 imput amplifier is a better choice (I didn't test it yet).
As a conclusion, do not expect this circuit to work, as is, in any conditions and do not think that without a scope you'll be able to make it work (unless you are very lucky, of course).
Jain


The video signal should be 1 v pp including the sync.
>For NTSC, the signal is measured in IRE with -40 IRE
>being the lowest point in the signal(the bottom of the
>sync) and 100 IRE being the highest point in the
>signal(brightest white in the video. 140 IRE units is
>equal to 1v pp. If the video is clamped correctly,
>-40 IRE should be -.286 vdc, 0 IRE(or the blanking
>level) should be 0v pp, +7.5 IRE(black level) should
>be .054v pp and 140 IRE(white level) should be
>.714vdc. The signal from the IF is not usually
>clamped to the specification and it doesn't make a
>difference since the signal passes through a cap
>anyway. Regardless, the 3chip is looking for a 1v pp
>signal, including the sync. Since the sync is raised
>in a scrambled signal, the total peak to peak value of
>the scrambled signal would consist of the video. The
>size of the negative falling edge of the sync
>determines the width of the NED. The falling edge of
>the NED locks to the start of the "A" section. This
>is for Rev7t1a code and NTSC. The width of the NED
>should be 1-1.8 us, if I remember right.

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