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Date Posted: 11:37:51 01/01/04 Thu
Author: Phil Q.
Subject: Re: Question for Phil Q
In reply to: Virtuax 's message, "Re: Question for Phil Q" on 07:40:43 01/01/04 Thu

Guys,

Replacing CLRF SPLITCOUNT with ANDWF SPLITCOUNT,0 really won't do anything except stop the code from resetting the split-sync counter for each frame. Here's how it works:

From lines 24-26, if split-sync is seen a line then SPLITCOUNT is incremented. After that, bit 1 of SPLITCOUNT is checked to see if it is set. If bit 1 is set then at least two instances of split-sync have been detected and inverted video is assumed. Looking at the last two bits of SPLITCOUNT:
First, the register is cleared so they would start as 00
After the first increment: 01 (bit 1 still clear)
after the next increment : 10 (bit 1 set now)
after another increment : 11 (bit 1 still set)

If you don't clear the register each time, the next increment will roll the last two bits over to 00. Doing an ANDWF SPLITCOUNT,0 will take the contents of W (which contains a 1 after returning from MAKEHLINE) and AND it with the current contents of SPLITCOUNT. Bit 1 would be cleared by this but the state of bit 0 would be unknown. It doesn't matter though, because putting a zero as the destination parameter of the ANDWF instruction means that the result of the instruction will be stored back to W, NOT SPLITCOUNT.

Sounds like you're on the right track with line 21 though, the info I have on the system shows relevant edges on lines 16 and 260, either it's inaccurate or they can move things around. I've always wondered why they didn't encrypt the mode change info in the data stream, if you're seeing a flag for inversion on line 21 then perhaps they're at least embedding it there. I would concentrate on either the line 21 info or the NED data. Unfortunately we have DirecTV now so I can't be of much assistance with looking at the data and trying code changes but at least I can help keep you from wasting your time.

Cheers,

- Phil



>HI JV,
>
>IŽll check line 21 again, if I remember that code
>appears on all scrambled channels, Did you fixed video
>only changing the code on line 21??? Could you post
>here what you made???
>I replaced all zenith code with "NOP" and REV7TD2 is
>still working.
>As I posted here only when "CLRF SPLITCOUNT" was
>replaced by "ANDWF SPLITCOUNT,0" almost fixed the
>code, as IŽm not a programmer I dont know how to
>change FUZZY COUNTER to fix the code.
>The 2 level random DC start on line 16 (split-sync)and
>finish at line 259.You need to remove capacitor AGC
>hack to see the flickering, cause this DC restore
>circuit change frame by frame his off-set.
>There are 2 NED for normal burst and 4 for DC shifted
>frame,
>PED dont change, so "SPLITCOUNT" make wrong decision
>for SAInvert.
>
>Happy New Year
>
>Virtuax
>
>
>>Hi Virtuax,
>>
>>I've notice that at line 21 they send a lot of DATA, I
>>changed the code to look at an specific NED into this
>>line, this NED appears only when the video is sent
>>inverted, so I change the video mode, when this NED
>>doesn't appear I assume that is Normal video.
>>It works very well but I'm getting an brighter image
>>when the mode is inverted, do you have an idea to
>>adjust this..???
>>
>>TKS,
>>
>>JV
>>
>>>Hey Phil,
>>>
>>>JVL are rigth Phil , changing line 450 didnt work
>>>(sorry I was not so clear ), I made up to 300 changes
>>>and thereŽs only one that almost worked, when change
>>>from "CLRWF SPLITCOUNT" to "ANDWF SPLITCOUNT,0" now
>>>lock but to instable and loss SAInvert detect, some
>>>time inverted, I think this is a starting point for
>>>code adjusments.
>>>Ps. need change channel up & down many times to work.
>>> Doing that change you IŽll see a fickering video,
>>>cause they changing line 16 (split-sync) with 2
>random
>>>DC level.
>>>IŽm looking here to:
>>>(http://www.piclist.com/techref/microchip/edgedetect.
>h
>>t
>>>m) a way to detect edge events.
>>>
>>>
>>>
>>>Virtuax

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