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Subject: A Startup Looking for IC Layout Designer/Lab Technician


Author:
Sherry
 		[ Next Thread | Previous Thread | Next Message | Previous Message ]
Date Posted: 17:18:04 10/09/02 Wed
Job Requirements:

- Minimum 5 years experience with layout of high performance digital CMOS
circuits
Preferred
- Extensive knowledge of Cadence Virtuosos - version 4.3 or 4.4, and
database
management preferred
Will consider experience with other UNIX based layout editor such as Mentor
Graphics ICGraph
- Expertise in running and interpreting results of physical design
verification.
Direct experience with Mentor Graphics Calibre verification or similar
hierarchical tool preferred.
- Cadence SKILL language is a plus.
- Experienced with creation and implementation of complex layout
methodologies in a
team environment.
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Replies:
Subject Author Date
Re: A Startup Looking for IC Layout Designer/Lab TechnicianRay D. Espiritu00:58:02 12/27/02 Fri
Re: A Startup Looking for IC Layout Designer/Lab TechnicianIsmayil Arafath04:57:43 03/25/03 Tue

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