Author:
Warren F. Szczypiorski
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Date Posted: 16:10:44 12/28/02 Sat
In reply to:
Lary
's message, "Senior IC Layout Designer" on 15:50:37 04/22/02 Mon
RESUME
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WARREN F. SZCZYPIORSKI
1239 WOODSIDE RD.
COSHOHOCKEN, PA. 19428
610-825-5469
Email: warrensz@earthlink.net
POSITION DESIRED: VLSI LAYOUT DESIGN ENGINEER
EMPLOYMENT HIGHLIGHTS:
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@ ATI RESEARCH INC.
6 TERRY DR.
NEWTOWN, PA. 18940
215-860-7500
DEC 97 TO PRESENT
FULL CUSTOM LAYOUT/DESIGN OF HIGH SPEED ANALOG AND DIGITAL CIRCUITS
IN SUB MICRON TECHNOLOGY FOR THE GRAPHICS CHIP INDUSTRY. EFFORTS INCLUDED
PHYSICAL DESIGN OF DATAPATHS, MEMORIES, STANDARD CELL LIBRARIES AND PLACE
AND ROUTE SUPPORT.
TOOLS: CADENCE (OPUS/DFII), CALIBRE AND DRACULA
HIGHLIGHT: TWO PATENTS AWARDED
@ TSENG LABS INC.
6 TERRY DR.
NEWTOWN, PA. 18940
215-968-0502
JUNE 95 TO DEC 97
CUSTOM VLSI LAYOUT DESIGN OF HIGH SPEED GRAPHICS CHIPS IN DEEP
SUB-MICRON TECHNOLOGY. CIRCUITS WERE OF MIXED SIGNAL VARIETY. GENERATED
CUSTOM DATAPATHS, STANDARD CELL LIBRARIES, MEMORIES ETC. RESPONSIBLE
FOR DRC, ERC AND LVS, AS WELL AS RUNSET RUNSET GENERATION. DUTIES ALSO
INCLUDED P&R SUPPORT SCHEMATIC CAPTURE AND SPICE EXTRACTION, AS WELL
AS TRAINING OF PERSONELL.
TOOLS: CADENCE (OPUS/DFII), DRACULA, ARCADIA, CELL ENSEMBLE,
CELL3 AND TANNER.
@ ATT (BELL LABS.)
UNION BLVD.
ALLENTOWN,PA.
NOV. 93 TO JUNE 95
CUSTOM LAYOUT OF MIXED SIGNAL INTEGRATED CIRCUITS. RESPONSIBLE
FOR SCHEMATIC CAPTURE, LAYOUT AND VERIFICATION AND PARASITIC EXTRACTION.
TOOLS: (ATT INTERNAL) SCHEMA, GRED, LTX, LARC, GOALIE AND GEMINI
@ HARRIS SEMICONDUCTOR
RT 202, SOMMERVILLE N.J.
CONSULTANT
JUN. 93 TO NOV. 93
CUSTOM LAYOUT AND VERIFICATION OF BICMOS INTEGRATED CIRCUITS
FOR THE AUTOMOTIVE ELECTRONICS INDUSTRY.MODIFY AND REVERIFY EXISTING
PRODUCT LINES.
TOOLS: CADENCE EDGE AND DRACULA.
@ VLSI TECHNOLOGY INC.
PRINCETON, N.J.
CONSULTANT
JUN. 93 TO NOV. 93
GENERATED COMPLEX DATAPATHS, MODIFY EXISTING CIRCUITS AND SUPPORT
PLACE AND ROUTE EFFORTS.
TOOLS: COMPASS DESIGN AUTOMATION
HIGHLIGHTS CONTINUED:
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@ COOMODORE BUSINESS MACHINES
WEST CHESTER, PA.
JAN. 92 TO JUN. 93
CUSTOM VLSI LAYOUT SPECIALIST RESPONSIBLE FOR THE LAYOUT AND
VERIFICATION OF HIGH-PERFORMANCE IC'S FOR THE COMPANYS'AMIGA PRODUCT
LINE. EFFORTS INCLUDED CELL LIBRARY AND PLA GENERATION.
TOOLS: CALMA GDSII, VALID CONSTRUCT, SILVAR LISCO SCII AND
DRACULA.
@ INTEGRATED CIRCUIT SYSTEMS
VALLEY FORGE CORP. CTR.
VALLEY FORGE, PA.
JUN. 77 TO JUN. 87
SENIOR LAYOUT DESIGNER LATER TO BECOME DEPARTMENT MANAGER.
FULL CUSTOM IMPLEMENTATION OF CIRCUITS FOR FIRMS SUCH AS DIGTAL,
RCA, HUGHS AND MILTON BRADLEY. RESPONSIBILITIES INCLUDED HIRING AND
TRAINING.
@ MOS-TECHNOLOGY INC.
VALLEY FORGE, PA.
NOV. 70 TO JUN. 77
RESPONSIBLE FOR FULL CUSTOM IMPLEMENTATION OF VAROUS CIRCUTS.
NOTABLE WAS THEDEVELOPMENT OF THE FIRMS' CALCULATOR CHIP LINE WHICH
WAS PRODUCED IN VERY HIGH VOLUME.
@ GENERAL INSTRUMENT CORP.
HICKSVILLE, L.I.N.Y.
LAYOUT DESIGNER IN THE EARLIEST DAYS OF INTEGRATION. DEVELOPED
THE FIRMS' FIRST SILICON GATE PROCESS AND COLOR TV IC CHIPSET.
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@ ADDITIONAL: CONSULTING RELATIONSHIPS WITH FIRMS SUCH AS ENSONIQ CORP.,
QUIKPAK CORP. AND ALLIED SIGNAL CORP.
EXPERIANCED IN ELECTRO MECHANICAL (PRINTED CIRCUITS) DESIGN
@ FAMILIAR WITH UNIX ENVIRONMENT (AWK, VI & EMACS); PC'S (MS-DOS)
@ POSSESS HOME OFFICE ENABLING ME TO ACCOMPLISH DESIGN TASKS AT HOME.
@ PERSONAL:
MARRIED, THREE CHILDREN
HIGH SCHOOL GRAD & ADDITIONAL TRAINING IN ELECTRONICS TECHNOLOGY
HOBBYS - ANTIQUE RADIO RESTORATION, MARINE AQUARIA
@ REFERENCES AVAILABLE ON REQUEST
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