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Date Posted: 05:41:58 11/28/01 Wed
Author: Potter
Subject: Re: AGC fix Schematic
In reply to: Jain 's message, "Re: AGC fix Schematic" on 19:11:36 11/27/01 Tue

I came up with a similar 2 chip descrambler for the 5508 box originally (dual monostable and support) which worked (sortof) but could not deal with random inversion and was quite unstable - used a couple of convenient signals generated within the box. Since building a 3chip (PIC) type decoder I never looked back except to what's in the data packet which normally controls the box.
Any 'standard' 3chip decoder will work with the appropriate code changes so, like me, you'll need to very closely check the signal on a cro to work it out. If the vsync is normal the LOCKON routine will work as long as you are looking for edges of the correct polarity. MAKEVBI determines whether lock is maintained by looking for an edge in a ~2usec window - usually both polarities are OK. MAKEHLINE is the routine which adjusts the timing either in code (add/remove cycles/line) or by driving a vcxo circuit based on a high voltage zener's voltage dependant variable capacitance characteristic.
You say the Hsync is suppressed - is it visible at all and if so, inverted as well? if at all visible the edge detectors will respond to it if sensitive enough. The code needs to look for edges of the correct polarity and the edge check for maintaining lock can be done at either end of the Hsync pulse, I found the trailing edge is better for my system (50Hz PALB/G) which has a very large inverted Hsync. There is also a possibility of split sync which needs special handling.
My best advice is to become familiar with PIC code (only 35 instructions to learn) and look at the many code examples available, use spare ports to trigger the cro at interesting points in the video frame and it will all fall into place.

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