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Date Posted: 07:38:53 02/13/02 Wed
Author: Jain
Subject: Re: AGC sampling added to Rev7t1d2
In reply to: Potter 's message, "Re: AGC sampling added to Rev7t1d2" on 07:12:56 02/13/02 Wed

Clear now! Lucky you and your code...
NTSC users have to wait someone interested to change the code the same way, maybe even to let the unscrambled channels pass as they are... (I'm realy sorry I do not know how to do it).
Cheers
Jain

>In my code only the syncs are manufactured and during
>the VBI which is normal (thanks to my provider) I
>simply pass the colour burst and blank lines straight
>through the 'normal' gate with no modification so the
>sampling logic only needs to exclude the Hsync itself
>to get an average level.
>
>>OK Potter, you say:"...to sample the uninverted black
>>part of a quiet line...".
>>My question is: durring the sampling period of time,
>>except the sampling gate, which other gate is open, so
>>that is bringing the refference black level of the
>>signal (the 'normal' gate is suppose to be the one,
>>but you didn't mention it; that 'normal' gate, unless
>>the code is modiffied, is closed durring VBI, so it
>>couldn't provide any kind of signal).
>>Jain
>>
>>>In my case the outputs of the 4066 are capacitively
>>>coupled to the amp and I used the 'burst' gate as it
>>>was free ( in the current version) to sample the
>>>uninverted black part of a quiet line - the same one
>>>being sampled for AGC. There was little difference
>at
>>>first but the clamping level is now 'dynamic' and
>>>adapts itself as I change channels or the signal
>>>strength varies.
>>>A concern is that the circuit is sampling its own
>>>output minus the drop across a 1N4148 and improvement
>>>would need some gating so that the sample is the true
>>>uncompromised black level of the original signal -
>>>maybe taking the sample from the output of the LM733
>>>to provide DC separation of input & output (10uF cap
>>>coupling to the 4066).
>>>
>>>>I studdied the solution for dc restoration and I'm
>>not
>>>>sure is doing the right thing. The point where from
>>>>the circuit is sampling the dc level doesn't sounds
>>>>right. It means you have to sample the real black
>>>>level of the signal, not the black level set in 3
>>chip
>>>>(let's note that the input at the sampling circuit
>is
>>>>the same --determined by the ratio of the two
>>>>resistors in the base of the first transistor in the
>>>>output amplifier-- during the sampling period; there
>>>>is no other switch open in the same time, provided
>>the
>>>>code was not modified to open the normal one). Also,
>>>>the black level will always depend on the amplitude
>>of
>>>>the synchro pulse, witch is set by 3 chip at the
>same
>>>>level, no matter the real level of the signal
>comming
>>>>from IF IC (that's why I proposed rethinking the
>idea
>>>>of shifting the real blanking portion of the signal
>>>>instead of inserting an artificial synchro, but it
>>>>seems everybody is hapy with the actual results...).
>>I
>>>>am still thinking which is the right way to do it.
>>>>Jain
>>>>
>>>>Jain
>>>>
>>>>>I tried the DC restore today on the 50MHz SX board
>>>and
>>>>>it seems to work fine using my AGC control pulse.
>>>>>Couldn't get a better result than with the 5k pot
>>>>>though which may just mean that it was already as
>>>good
>>>>>as I could get it.
>>>>>I tried with LM358 as specified and a TL072 and the
>>>>>result was the same.

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